Buffer circuits, or amplifier circuits, provide electrical impedance transformation from one circuit to another. The buffer circuits can be configured with a desired input-output ratio (gain) and with a particular bandwidth. The gain can be unity or be less or more than unity. The gain can also be negative or positive. The bandwidth can be determined from a frequency range over which the gain of the buffer circuit is within a particular range. Unless otherwise stated, the bandwidth corresponds to a 3 decibel (db) range in the gain.
A particular type of buffer circuit is a common mode logic (CML) buffer that can be used in connection with high-speed signals that are used in wireless communication systems, serial data protocols, and other high-speed signaling solutions. A particular application for CML buffer circuits includes, but is not limited to, programmable logic devices (PLDs).
Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.